Semi-conductor components, e.g. corresponding integrated (analog and/or digital) computing circuits, semi-conductor memory components such as for instance function memory components (PLAs, PALs, etc.) and table memory components (e.g. ROMs or RAMs, particularly SRAMs and DRAMs), etc. are subjected to numerous tests in the course of the manufacturing process.
For the simultaneous manufacture of a plurality of (generally identical) semi-conductor components, a so-called wafer (i.e. a thin disk consisting of monocrystalline silicon) is used. The wafer is appropriately processed (e.g. subjected to numerous of coating, lighting, etching, diffusion implantation process steps, etc.), and subsequently sawn up (or e.g. scored and snapped off), so that the individual components are made available.
During the manufacture of semi-conductor components (e.g. DRAMs (Dynamic Random Access Memories and/or dynamic Read/Write memories), particularly of DDR-DRAMs (Double data Rate-DRAMs and/or DRAMs with double data rate)) the components (still on the wafer and incomplete) may be subjected to corresponding test procedures (e.g. so-called kerf measurements at the scoring grid) even before all the required above processing steps have been performed on the wafer (i.e. even while the semi-conductor components are still semi-complete) at one or several test stations by means of one or several test apparatuses.
After the semi-conductor components have been completed (i.e. after all the above wafer processing steps have been executed) the semi-conductor components are subjected to further test procedures at one or several (further) test stations—for instance the components—still present on the wafer and completed—may be tested with the help of corresponding (further) test apparatuses (“disk tests”).
In similar fashion several further tests may be performed (at corresponding further test stations and by using additional corresponding test equipment) e.g. after the semi-conductor components have been installed in corresponding semi-conductor-component housings, and/or e.g. after the semi-conductor component housings (together with the semi-conductor components installed in them) have been installed in corresponding electronic modules (so-called “module tests”).
During the testing of the semi-conductor components (e.g. during the above disk tests, module tests, etc.), so-called DC tests and/or e.g. so-called AC tests may be applied as test procedures.
During a DC test for instance a voltage (or current) at a specific—in particular a constant—level may be applied to a corresponding connection of a semi-conductor component to be tested, whereafter the level of the—resulting—currents (and/or voltages) is measured—in particular tested to see whether these currents (and/or voltages) fall within predetermined required critical values.
During an AC test in contrast, voltages (or currents) at varying levels, particularly corresponding test pattern signals, can for instance be applied to the corresponding connections of a semi-conductor component, with the help of which appropriate function tests may be performed on the semi-conductor component in question.
With the aid of above test procedures, defective semi-conductor components and/or modules can be identified and then eliminated (or else partially repaired), and/or the process parameters—used during the manufacture of the components in each case—can be appropriately modified and/or optimized in accordance with the test results achieved, etc., etc.
In case of a plurality of applications—e.g. at server or work station computers, etc., etc.—memory modules with data buffer components (so-called buffers) connected in series, e.g. so-called “buffered DIMMs”, may be installed.
Memory modules of this nature generally contain one or several semi-conductor memory components, particularly DRAMs, (e.g. DDR-DRAMs) as well as one or several data buffer components (e.g. corresponding DDR-DRAM data buffer components as standardized by Jedec)—connected in series before the semi-conductor memory components.
These data buffer components may for instance be installed on the same printed circuit board (card) as the DRAMs.
The memory modules are connected—particularly by interconnecting a corresponding memory controller (e.g. arranged externally to the memory module in question)—with one or several micro-processors of that particular server or work station computer, etc.
In “partially” buffered memory modules the address and control signals—e.g. those emitted by the memory controller, or by the processor in question—may be (briefly) buffered by corresponding data buffer components, and correspondingly similar address and control signals may be relayed—in chronologically co-ordinated, or where appropriate, in de-multiplexed fashion—to the memory components, e.g. DRAMs.
In contrast, the (useful) data signals—emitted by the memory controller and/or by the respective processor—may be relayed directly—i.e. without being buffered by a corresponding data buffer component (buffer)—to the memory components (and—conversely—the (useful) data signals emitted by the memory components may be directly relayed to the memory controller and/or the respective processor).
In “fully buffered” memory modules in contrast, the address and control signals exchanged between the memory controller (and/or the respective processor), and the memory components, and also the corresponding (useful) data signals can first be buffered by corresponding data buffer components, and only then relayed to the memory components and/or the memory controller (or to the respective processor).
For storing the data, especially corresponding test (result) data generated during the above test procedures (or any other test procedure), suitable special test data registers may be provided on the semi-conductor components tested in each case (e.g. on the above analog and/or digital computing circuits, or on the above semi-conductor memory components (PLAs, PALs, ROMs, RAMs, especially SRAMs and DRAMs, e.g. DDR-DRAMs, etc.).
The test data stored in the respective test data registers can be read from the test data registers by applying a corresponding special test data read control signal and corresponding address signals.
The above special test data read control signal has the effect that—in contrast with the use of an ordinary read signal—it is not the memory cells provided in the normal (useful data) memory region of the respective semi-conductor component that are being addressed with the help of the above address signal, but rather corresponding test data registers exactly specified by the relevant address signal.
If, for example, the above buffered memory modules (“buffered DIMMs”) are subjected to an appropriate module test, the problem could occur that the above test data read control signal would not be supported by the protocol of the respective data buffer components used.
This has the effect that test (result) data stored on the test data registers of each semi-conductor memory component may not be able to be emitted.
A correspondingly similar problem may occur when corresponding test data—from an external source—needs to be input.